In standard silicon complementary metal oxide semiconductor (CMOS) technology, p-type field effect transistors (pFET) use a boron (or other acceptor) doped p-type polysilicon layer as a gate conductor that is deposited on top of a silicon dioxide or silicon oxynitride gate oxide layer. The gate voltage is applied through this polysilicon layer to create an inversion channel in the n-type silicon underneath the gate oxide layer.
For a pFET to work properly, the inversion should begin occurring at slightly negative voltages applied to the polysilicon (poly-Si) gate conductor. This occurs as a consequence of the band alignment for the gate stack structure as depicted in FIG. 1. Specifically, FIG. 1 shows the approximate band alignment across a poly-Si/gate oxide gate stack in a typical pFET at zero gate bias. In FIG. 1, Ec, Ev and Ef are the conduction band edge, valence band edge and the Fermi level in the silicon, respectively. The poly-Si/gate oxide/n-type silicon stack forms a capacitor that swings into inversion at around 0 V and into accumulation around +1 V (depending on the substrate doping). The threshold voltage Vt, which can be interpreted as the voltage at which the inversion starts occurring, is therefore approximately 0 V and the flatband voltage Vfb, which is the voltage just beyond which the capacitor starts to swing into accumulation, is approximately +1 V. The exact values of the threshold Vt and flatband voltages Vfb have a dependence on the doping level in the silicon substrate, and can be varied somewhat by choosing an appropriate substrate doping level.
In future technology, silicon dioxide or silicon oxynitride dielectrics will be replaced with a gate material that has a higher dielectric constant. These materials are known as “high k” materials with the term “high k” denoting an insulating material whose dielectric constant is greater than 4.0, preferably greater than about 7.0. The dielectric constants mentioned herein are relative to a vacuum unless otherwise specified. Of the various possibilities, hafnium oxide, hafnium silicate, or hafnium silicon oxynitride may be the most suitable replacement candidates for conventional gate dielectrics due to their excellent thermal stability at high temperatures.
Unfortunately, when p-type field effect transistors are fabricated using a dielectric such as hafnium oxide or hafnium silicate, it is a well known problem that the flatband voltage Vfb of the device is shifted from its ideal position of close to about +1 V, to about 0+/−300 mV. This shift in flatband voltage Vfb is published in C. Hobbs et al., entitled “Fermi Level Pinning at the Poly-Si/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers. Consequently, the threshold voltage Vt of the device is shifted to approximately −1 V. This threshold voltage Vt shift is believed to be a consequence of an intimate interaction between the Hf-based gate oxide layer and the polysilicon layer. One model (See, for example, C. Hobbs, et al., ibid.) speculates that such an interaction causes an increase in the density of states in the silicon band gap at the polysilicon-gate oxide interface, leading to “Fermi level pinning”. The threshold voltage Vt therefore is not in the “right” place, i.e., it is too high for a useable CMOS (complementary metal oxide semiconductor) technology.
It had been shown recently that the threshold voltage Vt shift resulting from the incorporation of the high k gate dielectric can be considerably controlled using a thin (5–15 Å) insulating interlayer, such as aluminum nitride (AlN), between the high k dielectric (HfSiO) and the polysilicon gate conductor. FIG. 2 depicts the capacitance v. voltage plot of a pFET device having a 2.5 nm thick SiO2 dielectric layer (control), as indicated by reference number 1; a pFET device having a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer, as indicated by reference number 2; and a pFET device having an AlN insulating interlayer atop a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer, as indicated by reference number 3.
Still referring to FIG. 2, comparison of the capacitance v. voltage plot for the pFET with 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer to the capacitance v. voltage plot for the pFET device having an AlN insulating interlayer atop a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer reveals a positive shift of approximately 400 mV in the threshold voltage Vt and the flatband voltage Vfb of the pFET device incorporating the AlN insulating interlayer, wherein the threshold Vt and flatband voltages Vfb are shifted towards their operating values. The effects of the insulating interlayer on the threshold voltage Vt in pFET devices is discussed in greater detail in co-pending and co-assigned U.S. patent application Ser. No. 10/845,719, entitled ALUMINUM NITRIDE BASED THRESHOLD AND FLATBAND VOLTAGE PRESERVATION LAYER IN POLYSILICON BASED P-TYPE FILED EFFECT TRANSISTORS, filed May 14, 2004, the entire content and subject matter of which is incorporated herein by reference.
However, applicants have determined that the presence of the AlN insulating interlayer between the polysilicon gate conductor and high k dielectric in nFET devices disadvantageously results in a positive threshold voltage Vt shift, as shown in FIG. 3. FIG. 3 depicts capacitance v. voltage curves for an nFET device comprising a 2.5 nm thick SiO2 dielectric layer (control), as indicated by reference number 1′; an nFET device comprising a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer, as indicated by reference number 2′; and an nFET device comprising an AlN insulating interlayer atop a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer, as indicated by reference number 3′.
Comparison of the capacitance v. voltage plot of the nFET device comprising an AlN insulating interlayer atop a 3.0 nm HfSiO high k dielectric atop a 1.0 nm SiO2 dielectric layer to the capacitance v. voltage plot for the nFET device comprising a 2.5 nm thick SiO2 dielectric layer (control) reveals a positive shift in the threshold voltage Vt, on the order of about 400 mV away from the capacitance v. voltage plot for the nFET device comprising a 2.5 nm thick SiO2 dielectric layer (control). The positive shift in the threshold voltage Vt due to the incorporation of the AlN insulating interlayer within the nFET device is an equally unfavorable characteristic as the original negative shift in the threshold voltage Vt of the pFET device, without the AlN insulating interlayer.
Prior methods to remove the AlN insulating layer from the nFET device region, without destroying the underlying nFET device region surface or removing the AlN insulating layer from the pFET device region, are not known. Prior etchants such as KOH or dry reactive etching techniques are undesirable due to their deleterious impact on the underlying high k dielectric.
In view of the above mentioned problem of controlling the threshold voltage Vt and flatband voltage Vfb shift, it has been nearly impossible to develop a high k gate dielectric CMOS technology that is capable of simultaneously stabilizing the threshold and flatband voltage Vt, Vfb for both nFET and pFET devices. As such, a method and structure that is capable of stabilizing the threshold voltage Vt and flatband voltage Vfb for both nFET and pFET devices containing a gate stack including a high k dielectric is needed.